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Faraday Technology Corp.
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FTGMAC100_S is a high-quality Ethernet controller with DMA function. It includes AHB wrapper, DMA engine, on-chip memories (TX FIFO and RX FIFO), MAC, and MII/GMII/RMII interface.
FTGMAC100_S is an Ethernet controller that provides AHB master capability and full compliance with IEEE 802.3 specification for 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 Mbps Ethernet. FTGMAC100_S supports MII/GMII/RMII interfaces. FTGMAC100_S DMA controller handles all data transfers between system memory and on-chip memories. With the DMA engine, this controller can reduce the CPU loading, maximize the performance, and minimize the FIFO size. FTGMAC100_S has on-chip memories for buffering, so that the external local-buffer memory is not needed. The MII and RMII interfaces support two specific data rates, 10 Mbps and 100 Mbps; while the GMII interface supports 1000 Mbps data rate.
- AHB bus interface supports bus master and slave modes
- DMA engine for transmitting and receiving packets
- Supports zero-copy data transfer
- Supports IP, TCP, UDP checksum offloads
- Supports IEEE 802.1Q VLAN tag insertion and removal
- Supports high priority queue for QoS and CoS applications
- Supports Wake-on-LAN function and three wake-up events: link status change, magic packet and wake-up frame
- Independent TX/RX FIFOs
- Supports half and full duplex (full duplex operation supported only in 1000 Mbps mode)
- Supports flow control for full duplex and back pressure for half duplex
- Supports MII/GMII/RMII interfaces
- Supports jumbo packets (9K bytes)
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