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Faraday Technology Corp.
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The FTMCP100 is a video and image compression/decompresion IP core that supports the MPEG-4 (ISO/IEC 14496-2) and JPEG (ISO/IEC 10918-1) related applications. The FTMCP100 includes the hardware engines to accelerate the computation-intensive tasks such as the motion estimation/compensation, DCT/IDCT, quantization/inverse quantization, AC/DC prediction, zigzag scan, and variable length coding/decoding. The FTMCP100 can be controlled by a CPU through the AHB 2.0 interface. By initializing the control registers of the FTMCP100, the motion estimation, and encoding/decoding pipeline of a macro-block can be done automatically. Thus, the CPU can be released from the timing critical tasks in the video and image encoding/decoding. The single-phase clock and the standard-cell-based approach allow you to quickly integrate the FTMCP100 into your SoC designs.
- Supports the AHB 2.0 interface
- Compliant with MPEG-4 (ISO/IEC 14496-2) simple profile L0 ~ L3 standard, with resolutions including subQCIF, QCIF, CIF, VGA, and 4CIF @ 30 fps in steps of 16
- Compliant with JPEG (ISO/IEC 10918-1) base-line standard
- Includes the hardware engines for the motion estimation/compensation, DCT/IDCT, quantization/inverse quantization, AC/DC prediction, and the variable length of coding/decoding
- A local memory controller to control the local memory shared by the CPU, FTMCP100, and DMA master
- A DMA controller to control the data transfers between the system memory and the local memory
- Automatic power down mechanism to reduce the power consumption
- Motion estimation search range: -16 ~ +15.5 (optionally -32 ~ +31) with the half-pel accuracy
- Supports 4 MV and unrestricted MV
- Rate control: Constant bit-rate control and variable bit-rate control
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