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Faraday Technology Corp.
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The FTMCP210 is a video compression IP core supporting ITU-T Recommendation H.264|ISO/IEC 14496-10 Advance Video Coding Standard (MPEG-4 part 10) baseline profile related applications. The FTMCP210 is a pure hardware engine with a built-in DMA engine to transfer data between system memory and local memory through AMBA® 2.0 AHB bus interface. The FTMCP210 can also be controlled by a host CPU through AMBA® 2.0 AHB interface. By initializing the control registers of the FTMCP210, a frame will be compressed into a bitstream. Thus CPU will service the encoder once per frame. The single-phase clock and standard-cell based approach allows you to quickly integrate the FTMCP210 into your SoC designs.
- Support AHB 2.0 interface
- Compliant with ITU-T Recommendation H.264|ISO/IEC 14496-10 Advance Video Coding Standard (MPEG-4 part 10) baseline profile Level 3.1 standard, with resolutions from 128x96 to 1280x720 @ 30 fps, with a step of 16
- Operation frequencies up to 160 MHz @ 0.18 μm process
- Encode D1 30 fps with 1 reference frame @ 50 MHz, 3 reference frame @ 90 MHz
- Pure hardware engine
- Built-in DMA engine to transfer data between system memory and local memory
- Automatic power down mechanism to reduce power consumption
- Motion estimation search range: -24 ~ +24 in horizontal direction, -16 ~ 16 in vertical direction with quarter-pel precision
- Rate control: constant bit rate control and variable bitrate control
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