Barco Silex 
Part Number : BA112JPEG2000E
Overview :
The BA112JPEG2000E IP core is a JPEG2000 hardware accelerator dedicated to image compression applications in either lossy or lossless environment with full support of the ISO/IEC 15444-1 specification (JPEG2000).
The core performs the computing-intensive operations of the normalized encoding process (also called Tier-1): the Discrete Wavelet transform, quantization and entropy encoding. The last part of the JPEG2000 encoding process, known as Tier-2 encoding (i.e. bit rate allocation and packet reordering), is more suitably achieved in software by the host processor.
Features : - Compliant with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
- Support for lossless and lossy compressions
- Parametric number of parallel entropy chains for improved compressed data throughput
- Rate and distortion metrics provided for rate allocation (Tier-2)
- Dynamically configurable encoder parameters:
- Wavelet filter type: 5/3 or 9/7
- Number of wavelet decompositions from 0 to 5 levels
- Tile size up to 128 by 128 and tile offset
- Code block size up to 32 by 32
- Pixel depth up to 12 bits in lossless mode (10 bits in lossy), pixel sign
- Entropy encoder with full support of JPEG2000 options
- One quantization factor per subband under mantissa/exponent format
- High-speed pixel interface allowing to transfer 1 pixel per clock cycle on a whole tile-component
- Easy interface to pixel input and compressed data output through simple synchronous protocol
- Encoder parameterization and control via synchronous host interface to external CPU
- Command and Control Interface for driving the encoder with limited or no CPU intervention
- Independent pixel and compressed interface clock domains for easy integration
- Fully synchronous design
- On-chip tile buffer for increased efficiency and reduced pinout
- Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz
Categories :
Portability :
Type : Soft
Deliverables : - RTL Code or netlist (depending on license type), Functional simulation testbench, Synthesis script, Full documentation
S2C: FPGA Base prototyping- Download white paper

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