Brace Design Solutions 
Short Desc. : BDS XPCI64 PCI IP core
Overview :
BDS XPCI64 PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI64 compatible PCI IP core.
Features : - Xilinx LogiCORE PCI64 compatible PCI IP core
- PCI Local Bus Revision 2.2 compliant
- 0 ~ 33MHz operation in Xilinx FPGAs
- Meets 33MHz PCI's setup (Tsu), clock-to-output (Tval), and hold (Th) time in supported Xilinx devices
- Supports Xilinx LogiCORE PCI64's standard three Base Address Registers (BAR), plus optional 3 more BARs and an Expansion ROM BAR
- Constraint files for Xilinx devices allows easy timing closure of the PCI IP core
- BDS PCI Testbench allows extensive verification by the user (Verilog HDL only)
- Includes Embedded RAM Controller 64 reference design (Verilog HDL only)
- Full VHDL support planned in the future
- Not hardware tested (Simulation only)
- The PCI IP core available in Xilinx NGO netlist or Verilog HDL RTL
- Verilog HDL RTL version allows the user to modify the PCI IP core or replace Xilinx LogiCORE PCI when converting to ASIC
- ISE WebPACK compatible
- Available for as little as $200 for non-commercial, non-profit, personal use
- Includes BDS XPCI32 PCI IP core and its reference designs
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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