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The CWda10 IP core is a stereo audio interface component designed to input a digital audio stream in the well known I2S interface format originally developed by Philips. The CWda10 contains an asynchronous FIFO whose input is clocked with the bit clock from the I2S interface, and whose output is clocked with a signal clk_out. An I2S input stage de-serializes the audio data. The samples are placed in the FIFO in parallel at twice the sample rate Fs (stereo). The destination user core may use an arbitrary clock signal (clk_out) to retrieve the audio samples in parallel from the FIFO.
- Compliant with the I2S standard
- Flexible Coreworks Audio Parallel Interface (CWAPI) at the output, which permits bridging to other standard interfaces (SPDIF-AES/EBU, IBM CoreConnectTM, AMBATM, etc)
- Double clock domain design with FIFO: output clock unrelated to the sample rate frequency Fs; clk_in; uses input bit clock from I2S
- Supports all commonly used sample rates.
- Supports up to 24 bits per sample.
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