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The CWda14 Configurable SPDIF-AES/EBU Receiver is a digital audio receiver IP core supporting the SPDIF, AES/EBU, AES3 and IEC60958 standards and also the IEC61937 and SMPTE 337M standards for non-PCM audio. The CWda14 receiver is able to extract the data from the SPDIF input using a fast clock whose frequency need not be related to the sample rate frequency Fs.
- Supports the IEC60958 (SPDIF), AES3, AES/EBU standards for PCM audio transmission.
- Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission.
- Purely digital solution for clock and data recovery requiring a system clock cw_clk unrelated to oksampling rate Fs.
- Supports any sample rates up to frequency cw_clk/540 including 32, 44.1, 48, 96 and 192 kHz.
- Measures input sample rate.
- Lock time less than 3 sub-frames.
- Reduced bandwidth by automatic removal of stuffing bits in non-PCM mode.
- Outputs jittery sample bit clock (average frequency 64xFs).
- Sample bit clock jitter can be attenuated with a 2nd order 100KHz cutoff frequency PLL to produce a good quality retransmission clock.
- Flexible Coreworks Link interface, which permits bridging to standard interfaces (I2S, IBM CoreConnect™, AMBA™, etc).
- Separate interfaces for data and control.
- Modular Structure using optional Add-on-Modules (AOM).
- Channel Status and User Data memory mapped buffers with programmable masks for change notification.
- Configurable audio data FIFO reporting the number of samples in FIFO and programmable almost full condition that can accessed trough the data CW-Link.
- I2S output interface that can be clocked using an internally extracted jittery clock, or an external jitter free clock that can be generated from the bitclk with a PLL.
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