||- Supports industrial standard Double Data Rate (DDR) and Double Date Rate 2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
- Page hit detection to support multiple column accesses within the same row.
- Pipeline access enables continuous data bursting and hidden active commands, even in the case of page misses.
- Issue precharge, active and read/write commands to multiple banks at the same time.
- Integrated data buffer captures and synchronizes SDRAM data using programmable delay cells or DLL.
- User controlled variable additive latency for DDR2 device.
- On-die termination (ODT) optimized for single and multiple SDRAM DIMM.
- Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
- Programmable SDRAM data width and user word size.
- Programmable SDRAM access timing parameters and burst length.
- Supports multiple external SDRAM banks.
- Automatic refresh generation with programmable refresh intervals.
- Self-refresh mode to reduce system power consumption.
- Optional ECC support.
- Designed with synthesizable HDL for ASIC and FPGA implementation.