Eureka Technology Inc. 
Part Number : EP532
Overview :
The EP532 DDR2 SDRAM Controller supports both Double Data Rate (DDR) and Double Data Rate 2 (DDR2) SDRAM devices. It is an interface between multiple DDR/DDR2 SDRAM devices and a memory requestor such as a processor or DMA device. This DDR II Controller allows the user logic to simply read from or write to the memory system without having to be concerned with specific SDRAM control and timing issues. The EP532 presents a simple and efficient protocol to the user while hiding the complicated SDRAM behavior.
Features : - Supports industrial standard Double Data Rate (DDR) and Double Date Rate 2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
- Page hit detection to support multiple column accesses within the same row.
- Pipeline access enables continuous data bursting and hidden active commands, even in the case of page misses.
- Issue precharge, active and read/write commands to multiple banks at the same time.
- Integrated data buffer captures and synchronizes SDRAM data using programmable delay cells or DLL.
- User controlled variable additive latency for DDR2 device.
- On-die termination (ODT) optimized for single and multiple SDRAM DIMM.
- Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
- Programmable SDRAM data width and user word size.
- Programmable SDRAM access timing parameters and burst length.
- Supports multiple external SDRAM banks.
- Automatic refresh generation with programmable refresh intervals.
- Self-refresh mode to reduce system power consumption.
- Optional ECC support.
- Designed with synthesizable HDL for ASIC and FPGA implementation.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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