Eureka Technology Inc. 
Part Number : EP505
Overview :
The EC Interface to SDRAM controller provides high speed SDRAM for the system. It features two access ports. One port interfaces directly to the EC interface and the other access port is optimized for system core logic such as DMA or PCI bus bridge.
The EP505 EC Interface-SDRAM controller contains a built-in arbitration unit to allow both the MIPS CPU and system core logic to share SDRAM access. Rotating priority scheme ensures equal sharing of the memory bandwidth.
Features : - Designed with synthesizable HDL for ASIC and PLD synthesis.
- SDRAM controller interface directly with MIPS EC interface and user interface.
- Built-in arbitration between two access ports.
- Second access port allows memory sharing with user logic devices.
- Dual write buffer for simultaneous write posting and SDRAM access.
- Address pipeline and separate read and write data phases are supported.
- Zero wait state burst data transfer on both MIPS EC interface and SDRAM.
- Operates on both discrete SDRAM chips and PC100/133 SDRAM DIMM.
- Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
- Pipeline access allows continues data transfer without wasted cycle.
- Fast page access on row address matching.
- Independent row address matching for each of the 4 SDRAM banks.
- Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
- Programmable SDRAM access timing parameters.
- Automatic refresh generation with programmable refresh intervals.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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