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The EP454 AMBA AHB to PCI host bridge is designed for interfacing the ARM CPU with the PCI bus and forward data access from both the upstream and downstream directions. The host bridge consists of three functional units: AHB bus slave, AHB bus master, and PCI interface. The AMBA AHB bus and the PCI bus can operate at two different clock domains.
Any bus mastering devices on the AMBA AHB bus can also access the host bridge. The core has multiple data buffers to achieve high speed data posting, prevent bus deadlock, and allow clock domain crossing for the data.
- Fully supports PCI specification 2.2 to 3.0 protocol.
- Supports AHB bus protocol, transfer size, burst size and response types.
- Downstream access allows AHB bus devices such as CPU to access PCI bus.
- Upstream access allows PCI bus devices to access system resources on AHB bus.
- AHB bus and PCI bus operate at independent clock domains.
- Total of six write buffers for write data posting for all interfaces.
- Supports AHB burst transfers up to 16 data words.
- Supports all AHB slave response types when functioning as AHB bus master.
- PCI interface includes bus master, bus target and configuration access initiation.
- Generates standard PCI type 0 and type 1 configuration accesses.
- Read access to PCI bus handled as delay read to prevent system deadlock.
- Automatic handling of configuration register read/write access.
- Includes all PCI specific configuration registers.
- User controlled base address register sizing and mapping.
- Retry counter to limit bus access to non-responsive target device.
- PCI status directly available to user logic for interrupt generation.
- Optional features include Address Translation, DMA, PCI bus arbiter, Cardbus, PCMCIA, MiniPCI, Power management, and Hot swap.
- Optimized for ASIC and PLD implementations, including on-chip ARM CPU.
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