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The EP140 is an AHB bus slave device designed to interface various user logic with the ARM CPU. It decodes the AHB address and dispatch the request to user logic through two user interface ports. The bus slave also regulates the data flow between all ports to optimize performance. Different user logic such as SDRAM controller, FLASH controller, PCI host bridge, DMA and UART can be connected to the AHB bus through the slave.
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to two sets of on-chip or off-chip modules.
- Four write buffers to process posted write.
- Dual read buffers to process CPU read.
- Read access to external bus handled as delay read to avoid system deadlock.
- Supports burst transfer and zero wait state to maximize data bandwidth.
- Supports data width of 8, 16 and 32 bits.
- Supports burst transfers up to 16 words of data.
- Supports early burst termination and CPU master busy.
- Multiple bus slave is supported by Ready signal input and outputs.
- Programmable address mapping to multiple address spaces.
- User interface optimized to access secondary bus such as PCI and memory subsystems based on SDRAM and FLASH.
- Optimized for ASIC and PLD implementations, including Excalibur PLD.
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