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 Eureka Technology Inc. 
Part Number : EC140
Overview :
The EC140 64-bit PCI bus target core is optimized for different applications. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. This 64-bit PCI target core utilizes double data buffer design approach which minimizes design gate count and achieves highest possible data bandwidth at the same time.
The EC140 64-bit PCI bus target is capable of handling both 32-bit PCI transfers and 64-bit PCI transfers. Based on the bus width chosen by the master, the EC140 bus target transfers data with the higher data width whenever possible.
Features : - Fully supports PCI specification 2.1 and 2.2 protocol.
- Supports both 64-bit and 32-bit bus systems.
- Supports dual address cycle (DAC) 64-bit addressing.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Combined bus master and target functions.
- Efficient back-end interface for different types of bus slave and master devices.
- Zero wait state burst data transfer.
- Automatic transfer restart on target retry and disconnect.
- High speed bus request and arbitration.
- Parity generation and parity error detection.
- Includes all PCI specific configuration registers.
- Optimized for devices with slow output enable control.
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: UltraPLL



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