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 Eureka Technology Inc. 
Part Number : EC220
Overview :
The EC220 32-bit PCI bus master/target core is optimized for different applications. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. This 32-bit PCI bus master/target core utilizes double data buffer design approach which minimizes design gate count and achieves highest possible data bandwidth at the same time.
The PCI bus master controller is capable of initiating memory or IO read and write upon back-end requests. The type of command and the burst size are specified by the user for each data transaction.
Features : - Compliant with PCI specification 2.2/2.3/3.0 protocol.
- Designed for ASIC and FPGA implementations in various system environments.
- Combines bus master and bus target functions in one core.
- Supports burst transfer to maximize memory bandwidth.
- Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
- Supports target retry, disconnect and target abort.
- Automatic transfer restart on target retry and disconnect.
- Concurrent bus master and target function.
- Write buffer for target write data posting to increase PCI bus performance.
- Responds to standard PCI configuration access.
- Supports all PCI specific configuration registers.
- User controlled base address register sizing and mapping.
- Retry counter to limit bus access to non-responsive target device.
- PCI status directly available to user logic for interrupt generation.
- Option for integrated DMA controller.
- Option for AMBA AHB and other CPU interface.
Categories :
Portability :
Type : Soft
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