||- Compliant with PCI specification 2.2/2.3/3.0 protocol.
- Designed for ASIC and FPGA implementations in various system environments.
- Combines bus master and bus target functions in one core.
- Supports burst transfer to maximize memory bandwidth.
- Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
- Supports target retry, disconnect and target abort.
- Automatic transfer restart on target retry and disconnect.
- Concurrent bus master and target function.
- Write buffer for target write data posting to increase PCI bus performance.
- Responds to standard PCI configuration access.
- Supports all PCI specific configuration registers.
- User controlled base address register sizing and mapping.
- Retry counter to limit bus access to non-responsive target device.
- PCI status directly available to user logic for interrupt generation.
- Option for integrated DMA controller.
- Option for AMBA AHB and other CPU interface.