Digital Blocks, Inc. 
Part Number : DB9000AHB
Overview :
The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a
microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD
panel. In an FPGA, ASIC, or ASSP device, typically the microprocessor is an ARM
processor and frame buffer memory is either on-chip SRAM memory or larger off-chip
SRAM or SDRAM. Figure 1 depicts the system view of the DB9000AHB TFT LCD
Controller IP Core embedded within an integrated circuit device.
Features : - Wide range of programmable LCD Panel resolutions:
- Maximum programmable resolutions of 4096x2048
- Horizontal pixel resolutions from 16 to 4096 pixels in 16 pixel increments.
- Example LCD Panel resolutions:
- 240x240, 240x320, 320x200, 320x240, 480x272
- 640x200, 640x240, 640x400, 640x480
- 800x600, 1024x768, 1280x1024
- Support for 1 Port TFT LCD Panel interfaces:
- 18-bit digital (6-bits/color) & 24-bit digital (8-bits/color)
- Programmable frame buffer bits-per-pixel (bpp) color depths:
- 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel
- 16, 18, bpp directly drive 18-bit LCD pixel
- 24 bpp directly drive 24-bit LCD pixel
- Color Palette RAM to reduce Frame Buffer memory storage requirements and AHB Bus bandwidth:
- 256 entry by 16-bit RAM, implemented as 128 entry by 32-bits
- Loaded via the Slave Bus Interface statically by the microprocessor or the
- Master Bus Interface dynamically with each frame by the DMA controller
- Programmable Output format support:
- RGB 6:6:6 or 5:6:5 on 18-bit digital interface
- RGB 8:8:8 on 24-bit digital interface
- Programmable horizontal timing parameters:
- horizontal front porch, back porch, sync width, pixels-per-line
- horizontal sync polarity
- Programmable vertical timing parameters:
- vertical front porch, back porch, sync width, lines-per-panel
- vertical sync polarity
- Programmable pixel clock:
- pixel clock divider from 1 to 128 of Bus Clock
- pixel clock polarity
- Programmable Data Enable timing signal:
- Derived from horizontal and vertical timing parameters
- display enable polarity
- Three memories:
- 16-word x 32 bit input FIFO, decoupling AHB bus & LCD panel clock rates. Integrated with DMA controller.
- 256-word x 16-bit Color Palette RAM
- 16-word output FIFO
- Power up and down sequencing support
- 9 sources of internal interrupts with masking control
- Little-endian, big-endian, or Windows CE mode
- Compliance with AMBA Specification (Rev 2.0)
- Fully-synchronous, synthesizable Verilog RTL core.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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