Dillon Engineering, Inc. 
Short Desc. : Pipelined FFT
Overview :
The Pipelined FFT architecture features a single butterfly computational unit per rank.The Pipelined FFT IP Core provides efficient continuous data FFT calculations at the rate of one point per clock cycle.
Features : - Any radix-2 length
- Variable length option for runtime per-transform length select
- Clock rates to 400MHz in Virtex-5
- Fixed or floating point math
- Efficient memory usage, useful for ASIC applications
- Continuous data processing
- Optimized butterfly structure in each rank, consumes and produces one point per clock cycle
- DIF has normal order input, out of order output
- DIT has out of order input, normal order output.
- Optional input or output buffer, for completely normal order I/O
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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