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A critical component in the majority of DSP systems is the sinusoid generator, commonly called a Direct Digital Synthesizer (DDS) or numerically controlled oscillator (NCO). These DDS functions while simple algorithmically presents numerous difficulties to hardware engineers tasked with implementing the function. For example, it is frequently a challenge to limit the memory consumed for high SFDR requirements and also to reach maximum clock performance in the device.
The DDS Compiler eliminates these difficulties and reduces implementation time to the push of a button. Furthermore, the tool provides users with the ability to make implementation trade-offs between DSP48, Block Memory and Logic in order to achieve the most optimum solution for a given system.
- Drop-in module for Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, Spartan-3A, Spartan-3A DSP, and Spartan-3E FPGAs
- Very high performance, including optimal and optional use of DSP48
- Sine, Cosine, or quadrature outputs
- Look-up table can be allocated to distributed or block memory
- Phase dithering or Taylor series correction options provide high dynamic range signals using minimal FPGA resources. SFDR range is 18 dB to 120 dB
- Phase dithering removes the spectral line structure associated with conventional phase truncation waveform synthesis architectures
- Support for 1 to 16 independent channels
- High-precision synthesizer with fine frequency resolution ( Hz @ fclk = 400 MHz, 34-bit phase accumulator)
- 4-bit to 20-bit two’s complement output sample precision
- Optional phase
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