Gaisler Research 
Short Desc. : GRFPU High-PerformanceFloating Point Unit
Overview :
The GRFPU is an IEEE-754 compliant ßoating-point unit, supporting both single and double precision operands.The advanced design combines high throughput with low latency, providing up to 250 MFLOPS on a 0.13 um ASIC process. The host interface is clean and versatile, simplifying the interfacing to processor pipelines and DSPs. The accuracy and convergence of the FPU algorithms have been proven mathematically, and the implementation has been validated with more than 20 million test vectors. Special test programs such as Testßoat, UCBTEST and IeeeCC754 has been used, as well as ßoating-point based application software.
Features : - IEEE-754 compliant, supporting all rounding modes and exceptions
- Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs, negate
- Data formats: single and double precision (32- and 64-bit ßoats)
- Fully pipelined, 3 clock cycles latency for all operations except divide and square-root
- Non-blocking parallel execution of divide and square-root operations
- Clean and versatile interface
- LEON FPU Control unit available
- Supports all SPARC V8 ßoating-point instructions
- 250 MHz (250 MFLOPS) on a typical 0.13 um standard cell process using less than 100 kgates
- 65 MHz (65 MFLOPS) on a Virtex-II FPGA using approximately 8,000 LUTs
- Fault-tolerant (FT) version available
Categories :
Portability :
Type : Soft

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