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 Fraunhofer Institute Integrated Circuits - CorePool 
Part Number : FHG_I2C
Overview :
The I2C-bus interface serves as a bidirectional on-chip communication interface between parallel-bus applications and the I2C-bus. The interface implements the I2C-bus protocol for master and slave applications. Its functional parameterization allows an application-specific implementation without hardware overhead.
Features : - * Parallel interface to master and slave applications with handshaking
- Parameterizable functionality (master/slave receiver/transmitter)
- Parameterizable address mode (7/10 bit)
- Parameterizable transfer rate (100-400 kbit/s)
- Separate ports for each functional block
- No data storage, which ensures uncorrupted data in case of transfer errors
- Technology independent (FPGA and ASIC)
- Silicon proven
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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