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Intelliga Integrated Design Ltd
Short Desc. :
Intelliga's LIN (Local Interconnect Network) Bus Controller
Intelliga's Local Interconnect Network (LIN) protocol controller core is specifically designed for integration within both ASIC and FPGA based IC technology. Its ultra-low gate count and flexible system interface makes it ideally suited to the LIN concept as a low cost accompaniment to the CAN bus in automotive applications. As standard, Intelliga's LIN core, iLIN, is supplied as a reference design that uses a synchronous 8-bit general-purpose micro-controller interface with minimal buffering for the transportation of message data.
- Standalone LIN Rev 1.2 compliant ASIC/FPGA design with flexible, segregated system interface that allows the user to decide the split between compile time configurability and software programmability
- Performs all MAC/PHY logical functions and provides a simple interface to LIN transceiver chips such as the Philips TJA1020
- Low core gate count, less than 3k ASIC gates with transport buffers and acceptance filters conveniently accommodated in the system interface.
- Noise immune sampler with configuration options, programmable synchronizer and baud rate prescaler
- Master and slave modes supported together with sniffing capability for network diagnostic purposes
- Basic LIN system interface supplied as standard, uses an 8-bit MCU programming port with single ID address filter and an interface for software ID lookup to support multiple "slave tasks"
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