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The Xelic SONET/SDH Concatenated High Order Path Processor Core (XCS3CPP) performs path overhead processing and pointer processing for contiguous concatenated SONET/SDH payloads types. The XCS3CPP contains independent transmit and receive processors with dedicated external path overhead ports and a generic register interface to provide flexible insertion and extraction capability. Incoming/outgoing data is transferred at an STS-3c/STM-1 rate using an 8-bit data bus operating at 19.44Mb/s.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCS3CPP core available under flexible single use licensing terms with netlist or source code deliverables.
- Supports bypass, loopback, and normal modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Compliant with ITU-T G.707 and Telcordia GR-253-CORE Specifications.
- Supports processing for contiguous concatenated SONET/SDH payloads types (STS-3c/STM-1).
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