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 Intelliga Integrated Design Ltd 
Short Desc. : Intelliga's CAN 2.0B Bus Controller Core
Overview :
The CAN core has been designed as a full hardware implementation which totally offloads the local CPU from the burden of bit level processing. It is a gate efficient and well partitioned design which makes it particularly suitable for integration within ultra low power devices. The Advanced Peripheral Bus (APB) interface gives an example of how the device can be connected in a multi-clock power saving system. In this case an asynchronous FIFO bridges the gap between the local processor clock domain and a power saving peripheral clock domain. An 8-bit MCU style interface is also included as an example of a minimal gate count implementation.
Features : - Full hardware solution
- Conformant to version 2.0A/B of the CAN specification
- Supports extended identifiers
- Performs all MAC functions
- Power saving clock domains partitioned between core and system interface
- Noise immune sampler
- Ultra-flexible generic interface
- Warning threshold
- Configurable synchronizer
- 8-bit MCU style interface
- 16-bit APB style interface
Categories :
Portability :
Type : Soft
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