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Short Desc. : PSPP1284 IEEE 1284
Overview :
The PSPP1284 core implements the IEEE 1284 interface. Software-programmable for the operation as a host or peripheral device, the core supports Compatible, Nibble, Byte, EPP, and ECP mode of operations and includes a configurable depth FIFO tightly coupled with the DMA engine for efficient data transfer in ECP mode. Full-speed data transfer can be performed by initializing the core in ECP operation mode with DMA transfer enabled, and waiting for an interrupt at completion. The core provides a solution for parallel ports that requires minimal software assistance.
Features : - Performs host or peripheral operation modes
- Full hardware support for all data transfer modes
- Enables software handshake for initialization, protocol negotiation and
- data transfer phases
- Performs automatic data transfer in Compatible, Nibble, Byte, EPP, and ECP
- modes
- Easily interfaces to CPUs through a generic bus interface
- Configurable-depth FIFO tightly coupled with internal DMA engine
- DMA capability in ECP mode of operation for full-speed data transfer
- Hardware support for Centronics and IEEE
- Compatible Busy_Strobe_Ack timing
- Provides fourteen architectural configuration registers
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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