Short Desc. : MPEG2 Video Decoder IP Core
Overview :
The MP2VDSD is a standard-definition MPEG-2 video decoder compliant with the Main Profile Main Level (MP@ML) functionality specified by the ISO/IEC 13818-1 and ISO/IEC 13818-2 standards. The MP2VDSD also supports MPEG1 constrained parameter set bitstreams and MPEG1 bitstreams that are not constrained parameter set bitstreams as long as the parameter values do not exceed the corresponding MPEG2 MPML values. The MP2VDSD meets the constraints of the ATSC/Grand Alliance and DVB format specifications regarding Main Level.
Features : - Supports ISO/IEC 1172 (MPEG1) and ISO/IEC 13818 (MPEG2) bitstreams
- Decodes MPEG2 MPML
- Supports 15 Mbps input bit rate
- Supports 24, 25, and 29.97 MHz frame rates
- Supports either 525 lines at 60 Hz or 625 lines at 50 Hz SD television system
- Supports frame sizes 720x480 at 30 frames/s or 720x576 up to 25 frames/s
- Supports progressive and interlaced source material (for interlaced material, both field and frame coding are implemented)
- Easily controlled by commands through a control bus interface to start tasks or stall the MP2VDSD
- Controllable for letter box, pan & scan, and 3:2 pull down support
- Easily integrated into system-on-chip using shared memory
- Error detection and error recovery
- User Data extraction
- Supports ES video streams
- Minimal CPU intrusion, required only between picture data
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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