||- XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
- Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M FPGA.
- Soft IP targeted to the LatticeECP2M programmable array implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
- 10 GbE Media Independent Interface (XGMII).
- Optional Slip buffers for clock domain transfer to/from the XGMII interface.
- Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction.
- XAUI compliant lane-by-lane synchronization.
- Lane deskew functionality.
- Interface with the high-speed SERDES block embedded in the LatticeECP2M that implements a standard XAUI.
- Optional standard compliant MDIO/MDC interface.
- ModelSim® simulation models and test benches provided for free evaluation