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Short Desc. :
H16550S: UART with FIFOs and Synchronous CPU Interface Core
The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16550S can be run in either 16450-compatible character mode or in 16550-compatible FIFO mode, where an internal FIFO relieves the CPU of excessive soft-ware overhead.
- Capable of running all existing 16450 and 16550a software
- Fully Synchronous design. All inputs and outputs are based on rising edge of clock
- In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
- Adds or deletes standard asyn-chronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled trans-mit, receive, line status and data set interrupts
- Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock
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