Short Desc. : Ethernet 1/10 Gigabit flexiMAC MACO Core
Overview :
The LatticeSCM Ethernet flexiMAC™ MACO™ IP core is a flexible packet framer and parser that can implement Layer2 (data link layer or MAC) functionality for various standards. The flexiMAC functionality complements the Layer1 (physical layer) multi-protocol functionality of the LatticeSCM Physical Coding Sublayer (PCS) and is implemented in MACO hard logic. This yields a complete Layer1/Layer2 solution for 1/10Gb Ethernet standards.
Features : - 1Gb Ethernet MAC (full duplex only) standard support.
- 10Gb Ethernet MAC standard support including clauses 46.3.3 (Error and Fault Signaling) of IEEE Draft P802.3ae (also known as reconciliation layer)
- IP provided in encrypted netlist
- ModelSim® simulation models and test benches available for free evaluation
- In 10Gb Ethernet mode, the TX flexiMAC will frequently back-pressure the TX client when there are less than two client clock (156MHz) cycles between consecutive packets written to the TX EBR interface. Similarly, 10Gb Ethernet mode requires a minimum Inter-Packet Gap (IPG) of 16 bytes between incoming RX XAUI packets if the client side of the MAC is to perform an RX to TX loopback.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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