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Short Desc. :
Serial RapidIO to AHB Interface IP Cores
Jennic's RapidIO system-level IP product line provides a complete range of fully integrated RapidIO interface solutions,
intended for integration into SoC semiconductor devices. The RapidIO interface standard has been developed primarily
for use in providing the interconnect between embedded processing units such as processors, DSPs etc as used in
networking applications such as wireless infrastructure and Storage Area Networks.
- Conforms to the RapidIO Interconnect Specification – Rev.1.3.
- Serial RapidIO interface capable of supporting full duplex data rates up to 10Gbps in each direction
- Serial RapidIO Interface
- * Utilises ASIC vendors PHY technology
- * Operates at 1.25, 2.5 or 3.125Gbaud per lane
- * Supports 4x and 1x operation
- Two Cores Available
- * Serial RapidIO to AHB Interface (Transparent)
- * Serial RapidIO to AHB Interface (Queue)
- Serial RapidIO to AHB Interface (Transparent)
- * Provides an efficient RapidIO interface for low bandwidth/control type applications
- * Uses host bus snooping to provide a transparent interface suitable for use in bridging applications
- * Support Input/Output NREAD, NWRITE, NWRITE_R, SWRITE and Maintenance transactions
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