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Short Desc. :
ECC Module Reference Design
This reference design implements an Error Correction Code (ECC) module for the LatticeEC™ and LatticeSC™ FPGA families that can be applied to increase memory reliability in critical applications. The ECC module provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes that provides better performance than typical Hamming-based SECDED codes. Several architecture options are identified that allow the user to optimally tailor the speed, resource utilization, and latency of the module implementation to their specific application requirements.
- SECDED capability implemented using an optimal odd-weight parity matrix that provides better performance
- than typical Hamming-based codes
- Directly usable code for a (72,64) SECDED module provided. Specifications provided for similar (22,16)
- and (39,32) modules
- Separate registered encoder and decoder modules to support optimized integration with user logic
- Optional pipelining implementation to provide increased maximum speed of operation
- Error insertion/error indication diagnostic capabilities
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