Part Number : CI3523cm
Overview :
This macro-cell is a fully differential high-speed low-power pipeline IQ
ADC core designed for 90nm 1P5M (thin metals) Chartered CMOS
technology, Low Power (LP) Process.
The ADC architecture employs 9 multi-bit pipelined stages to achieve
sampling rates above 80 MS/s with low power dissipation. Digital error
correction is employed to reduce DNL errors.
Features : - 10-bit Resolution
- 10MHz to 80MHz Conversion Rate
- 2Vpp / 1Vpp Differential Input
- Power Supply : 1.2V±10%
- Input Interface Power Supply:
- 2.5V±10%
- Internal References
- Dynamic Power Scaling
- Current Consumption:
- 70mA @ 80MHz
- 10.8mA @ 10MHz
- Core Cell Area: 0.89 mm2
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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