|This macro-cell is a fully differential high-speed low-power pipeline IQ
ADC core designed for 90nm 1P5M (thin metals) Chartered CMOS
technology, Low Power (LP) Process.
The ADC architecture employs 9 multi-bit pipelined stages to achieve
sampling rates above 80 MS/s with low power dissipation. Digital error
correction is employed to reduce DNL errors.