Short Desc. : DDR SDRAM Controller
Overview :
The DDR SDRAM uses double data rate architecture to achieve high-speed data transfers. DDR SDRAM (referred to as DDR) transfers data on both the rising and falling edge of the clock. This reference design provides an implementation
of the DDR memory controller implemented in a Lattice ORCA Series 4 FPGA device. This DDR controller is typically implemented in a system between the DDR and the bus master. Figure 1 shows the relationship of the controller between the bus master and the DDR. The bus master could be either a microprocessor like the Intel i960 or a user’s proprietary module interface.
Features : - Simplifies DDR command interface to standard system read/write interface.
- Internal state machine built for DDR power-on initialization and auto refresh.
- Read/Write cycle access time optimized automatically according to DDR timing spec and the mode it is
- configured to.
- Auto refresh is done automatically without bus master intervention.
- Easily configurable to support different CAS latency and burst length, by changing the parameters.
- Supports ORCA Series 4 devices.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy