Short Desc. : LatticeECP2/M 7:1
Overview :
Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVDS interface (also known as Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. In many of these applications, the practice
of using low-cost FPGAs for image processing has become quite common. In particular LatticeECP2™ and LatticeECP2M™ low-cost FPGAs are well-suited to support 7:1 LVDS standard. This document describes the requirements for implementing a 7:1 LVDS interface and the advantages of using the LatticeECP2/M in such an interface. By extension, support for the 7:1 LVDS interface in LatticeECP2/M devices proves the feasibility of hardware
implementation for all other LVDS source synchronous requirements as well.
Categories :
Portability :
Type : Soft
TrueCircuits: UltraPLL

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