Logic Design Solutions 
Part Number : MI2CS
Overview :
The MI2CMS macro implements a synchronous singlechip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt or polled handshake. It controls all I2C-bus specific sequences, protocol and timing. The I2C macro interface allows the parallel-bus microprocessor to communicate bidirectionnally with the
I2C-bus.This macro can be customized according to specific needs (application-specific requirement).
Features : - Single-chip synchronous I2C Slave Macro in FPGA (I2C is a trademark of Philips, Inc)
- Designed to be included in high-speed and high-performance applications
- Direct Connection to CPU register set
- Compliant with I2C-bus specification version 1.0
- Standard mode operation (100Kbits)
- Support for reads and writes only
- 7-bit and 10-bits address management
- Synchronised on system clock
- Hardware digital filter on SCL and SDA signals
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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