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Short Desc. : ARC® 625D processor
Overview :
The ARC® 625D processor core is a full-featured, mid-range embedded core with bestin-class speed, die area and power characteristics. It is designed as a complete processor solution for SoCs targeted at consumer, networking, automotive and other cost-sensitive markets.
The ARC 625D core’s flexible, configurable memory architecture makes it ideal for RTOS-based applications. Powerful DSP options enable it to perform more functions, eliminating separate logic or DSP blocks from the SoC. Optionally, custom instruction extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores.
Features : - CPU Architecture
- • 5-stage instruction pipeline
- • Static branch prediction
- • 32-bit data, instruction and address buses
- • Scoreboarded data memory pipeline to reduce data stalls
- • Single-cycle instruction CCM (Closely Coupled Memory), 1KB – 512KB
- • Single-cycle data CCM, 2KB – 16KB
- • Configurable instruction cache, 2KB – 32KB
- • Configurable data cache, 2KB – 32KB
- • Configurable endianness
- • Up to 32, two level interrupts

- ARCompact™ ISA
- • 16- and 32-bit instructions for high code density
- • No overhead for switching between 16- and 32-bit
- • Single-cycle instruction execution
- • Up to 128 dual or single operand instruction codes available for user-defined extensions
- • Up to 64 directly addressable core registers and 32 conditional execution codes
- • Flexible addressing modes

- Registers
- • 16 or 32 entry register file in base processor, extendible to 60
- • 26 general purpose registers, extendible to 54
- • 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval

- DSP Extensions
- • 16- and 32-bit MUL and MAC instructions
- • Parallel execution of MUL, MAC and other ALU operations
- • Saturating arithmetic instructions
- • Zero overhead loop support

- ARC XY Advanced DSP Subsystem
- • For more information, see ARC XY Subsystem product brief

- Power Management
- • Sleep mode via software instruction
- • Clock gating option
- • High efficiency pipeline
- • On-chip RAM controls

- Host Interface/Debug Features
- • Software and hardware breakpoints with cascadable triggers
- • JTAG interface to host tools
- • Debug host can access all registers and CPU memory
- • Supported by leading debuggers including Green Hills Software and MetaWare®

- System Interface
- • Configurable port complies with industry standard AMBA or BVCI
- • Slave interfaces exposed for loading optional instruction and data CCMs
Categories :
Portability :
Type : Soft
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