RF Engines 
Short Desc. : Rate Conversion
Overview :
RF Engines' fractional resampling cores for FPGA can be used to perform up-sampling or down-sampling of high-speed digital signals. The architectures are highly scalable, and support rate conversion of just one channel or thousands of channels simultaneously, whilst maintaining efficient use of silicon resources, and providing excellent filtering performance in order to mitigate the effects of aliasing.
Features : - Fractional architecture allows precise sample rate changes to sub-Hertz resolution
- Architectures available for up and down conversion
- Simultaneous resampling of multiple channels (potentially thousands)
- Resampling rates reconfigurable at run-time
- Multi-channel aggregate sample rates up to 180 MHz
- High performance filtering reduces aliasing effects
- Silicon usage minimised for each application
- Supported by bit-true Matlab models
- Xilinx and Altera FPGA devices supported
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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