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Short Desc. : Low Jitter Multipling PLL
Overview :
The PLL622 macrocell is a low jitter PLL to be used for the distribution of a high frequency clock within integrated circuits or where a frequency synthesis is required. It has been designed to satisfy the ITU-T G.783 recommendation for jitter (lower than 16 ps rms @ 622 MHz). To reduce the noise a fully differential structure has been realised and a novel idea for the VCO has been implemented.
Features : - Technical data:
- Macro cell size: 310 x 220 um2
- Power supply voltage range: 3.0-3.6 V
- Power consumption: 18 mW *
- Output clock jitter @ 622 MHz: 10 ps peak-to-peak *
- Duty cycle @ 622 MHz: 48 - 52 %
- Duty cycle @ 155-311 MHz: ~50 %
Categories :
Portability :
Type : Hard
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