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 Northwest Logic Inc. 
Short Desc. : DDR SDRAM Controller Core
Overview :

Northwest Logic’s Double Data Rate (DDR) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR SDRAM devices. The core also performs all initialization, re-fresh and power-down functions.

The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all DDR SDRAM configurations. The core also supports 2T timing.

Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is deliv-ered fully integrated and verified with the target DDR PHY. Northwest Logic supports a broad range of third party and its own soft DDR PHY. Contact Northwest Logic for more information.

Northwest Logic also provides IP Core customization services. Contact Northwest Logic for a quote.


Features : - Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
- Minimal latency achieved via pa-rameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports full rate and half-rate clock operation
- Full run-time configurable timing parameters and memory settings
- Supports 2T timing
- Full set of Add-On Cores available
- Delivered fully integrated and verified with target DDR PHY
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and Integration services available
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type :
 Hard IP 
Foundry :
Common Platform
Dongbu
Fujitsu
GlobalFoundries
Huali
IBM
Intel Corporation
LFoundry
Renesas
Samsung
Silterra
SMIC
TowerJazz
TSMC
UMC
X-Fab
Nodes :
14nm
16nm
20nm
28nm
32nm
40nm
45nm
55nm
65nm
80nm
90nm
110nm
130nm
150nm
160nm
180nm
250nm
350nm

Deliverables : - Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates
CST Webinar Series



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