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 Northwest Logic Inc. 
Part Number : Multi-Port_Front-End
Overview :

The Multi-Port Front-End Core provides a multi-port interface to Northwest Logic’s Memory Controller Cores.

Each user request is provided with its own request priority. The arbiter selects requests based on priority and then round robin arbitration. The arbiter can also perform Quality Of Service (QOS) based arbitration. In this mode, the arbitration results in each port receiving a specified amount of memory bandwidth. Each port also has a programmable time out period. Once a request times out, its priority is raised to the highest level ensuring its quick execution.

The Multi-Port Front-End Core includes the Multi-Burst Core. It automatically translates long burst requests into multiple requests matching the memory’s native burst length. This enables read or write requests of 256 data cycles or more. The Multi-Port Front-End Core can be used with or without the Multi-Burst Core. Northwest Logic will remove the Multi-Burst Core from a delivery upon request.

The Multi-Port Front-End Core can optionally include the Memory Test Core which performs address and data testing.

The Multi-Port Front-End Core can be used with the Reorder-Core to perform request reordering. The Reorder core rear-ranges the order of the requests coming from the Multi-Port Front-End to prioritize high priority requests and optimize memory throughput. This includes moving same bank/same row requests next to each other, same bank/ different row requests away from each other, moving reads next to reads and write next to writes. Data coherency is maintained during the reordering operation.

Northwest Logic also provides IP Core customization services. Contact Northwest Logic for a quote.


Features : - Provides a multi-port interface to Northwest Logic’s Memory Controller Cores
- Supports up to 32 user ports
- Performs priority and Quality Of Service (QOS) based arbitration
- Prevents request stalling using request timeout
- Automatically translates long burst requests into multiple re-quests matching the memory’s native burst length
- Memory Test and Reorder Core can be optionally added
- Achieves high clock rates with minimal routing constraints
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and Integration services available
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type :
 Hard IP 
Foundry :
Common Platform
Dongbu
Fujitsu
GlobalFoundries
Huali
IBM
Intel Corporation
LFoundry
Renesas
Samsung
Silterra
SMIC
TowerJazz
TSMC
UMC
X-Fab
Nodes :
14nm
16nm
20nm
28nm
32nm
40nm
45nm
55nm
65nm
80nm
90nm
110nm
130nm
150nm
160nm
180nm
250nm
350nm

Deliverables : - Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates
CST Webinar Series



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