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QualCore Logic, Inc.
Short Desc. :
V8101 - AHB
V8101 is an AHB based memory controller that can be interfaced with SDRAM, ROM, Flash and GPIO (General Purpose I/O) memory devices. The megacell acts as a slave on AHB bus.
The core provides all the functionality for read, write transactions from multiple masters to any interfaced memory device. The design makes the
AHB, free from the read, write latencies of the memory devices by split transaction support and thus increases the bus utilization.
- Supports eight memory devices of different types - SDRAM and CSI interfaces such as ROM, Flash and GPIO
- Addressing support upto 4GB memory
- AMBA-AHB, 32-bit compatible bus
- Support for AHB single beat, 4 beat and 8 beat wrapping bursts and Split transaction
- Read and Write data buffering
- APB Interface for configuration
- Upto 100MHZ SDRAM (32-bit) devices can be interfaced
- Supports byte and halfword writes to 32-bit SDRAM chips
- Transaction pipelining support with SDRAM
- Support for Auto-Refresh and Self-Refresh
- Paging Support for upto 4 open pages
- Parity generation and checking
- Support for interfacing with 8,16 and 32-bit CSI devices
- Burst read and write support for ROM and Flash interfaces
- Programmable read and write latency on a chip select basis
- Read Burst Accleration for burst capable ROMs
- Write byte enables for writing lower width data into higher width GPIO devices
- Provides support for two types of modes with GPIO devices - Address strobe mode and Handshake mode
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