The Cadence IP for MIPI M-PHY is a silicon proven, mixed-signal design IP, implemented on TSMC 28HPC process. It is engineered to quickly and easily integrate into any design, and to connect seamlessly to a Cadence, or third-party, RMMI compliant controller.
The MIPI-IP is designed to employ modular implementation with scalability for up to four lanes in one sub-link, offering great SoC flexibility. It is developed and has been extensively validated to reduce development risk and speed up time to market.
This M-PHY IP is a cost-effective, low-power solution for demanding mobile applications. Integrated functionality is the driver for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage. Developed and available early in the lifecycle of the most advanced semiconductor process nodes, the M-PHY IP is designed to be robust under varying signal strength and noise conditions.