Cadence Design Systems, Inc. 
Part Number : IP5602C
Short Desc. : MIPI M-PHY G2 TSMC 28HPC
Overview :

The Cadence IP for MIPI M-PHY is a silicon proven, mixed-signal design IP,  implemented on TSMC 28HPC process. It is engineered to quickly and easily integrate into any design, and to connect seamlessly to a Cadence, or third-party, RMMI compliant controller.
The MIPI-IP is designed to employ modular implementation with scalability for up to four lanes in one sub-link, offering great SoC flexibility. It is developed and has been extensively validated to reduce development risk and speed up time to market.
This M-PHY IP is a cost-effective, low-power solution for demanding mobile applications. Integrated functionality is the driver for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage. Developed and available early in the lifecycle of the most advanced semiconductor process nodes, the M-PHY IP is designed to be robust under varying signal strength and noise conditions.

Features : - Compliant to MIPI Specification for M-PHY v2.0
- Configurable as Type-I or Type-II MODULE
- Scalable up to four LANEs per SUB-LINK
- Slew-rate control for reduced EMI
- Matched analog design for low LANE-to-LANE skew
- Standard RMMI interface
- Mobile-optimized area and power
- Receiver supports terminated/unterminated operation
- Internal and external data-path loop-back modes
- Integrated BIST capable of producing and checking PRBS, CRPAT, and CJTPAT
Categories :
Maturity : Silicon proven
Portability :
Type : Soft
Deliverables : - GDSII macros with abstract in LEF
- Verilog post layout netlist
- STA scripts for use at chip or standalone PHY levels
- SDF for back-annotated timing verification
- Verilog testbench with memory model, configuration files, and sample tests

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