Cadence Design Systems, Inc. 
Part Number : IP6517E
Short Desc. : Octal SPI Flash Controller and PHY
Overview :

The Cadence IP for Octal SPI Flash Controller and PHY supports the fastest frequency at 200MHz, with DDR Mode and DTR Protocol (including Octal DDR protocol with DQS for Octal SPI Devices) enabling data transfer rates up to 400Mbps with reduced read latency including support for Octal DDR protocol with DQS for Octal SPI devices.
The integrated soft PHY enables the highest speed clock rates, while eliminating the need for a reference clock at 4 times (4x) the bus clockin SDR mode and an 8x clock in DDR mode. That simplifies the SoC design, reduces the complexity of additional clock domains, and reduces the power consumption by the OSPI bus.
Flash memory is being utilized more frequently in computers and electronic devices found in Automotive, IoT, Connected Home, and other emerging applications, which demand ever higher transfer rates and lower latency.  Expanding the flash Serial Peripheral Interface (SPI) accesses from the current 4 I/Os (Quad SPI) to 8 I/Os (Octal SPI) increased the Serial NOR Flash throughput and provide a more efficient solution for emerging applications, while providing backwards compatibility to QSPI devices with support for single, dual, quad, or octal I/O instructions.

Features : - Memory mapped ‘direct’ mode for XIP
- Software triggered ‘indirect’ mode for low latency data transfers
- DMA peripheral interface for indirect mode
- Up to 200MHz DDR (with DQS) for Octal SPI devices
- Up to 133MHz SDR or 80MHz DDR for Quad SPI devices
- Independent reference clock to decouple AHB clock from SPI clock – allows for slow system clocks
- Support for single, dual, quad, octal I/O instructions
Categories :
Tags : Octal, OSPI, QSPI, Flash, Controller
Maturity : Available on Request
Portability :
Type : Soft
Deliverables : - Clean, readable, synthesizable Verilog HDL
- Cadence Encounter RTL compiler synthesis scripts
- Verilog testbench with memory model, configuration files, and sample tests
- Documentation: integration and user guide, release notes

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy