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 Cadence Design Systems, Inc. 
Part Number : IP1046 LPDDR4 Controller
Short Desc. : DDR memory controller LPDDR4
Overview :

The Cadence Denali Controller IP for LPDDR4 is a configurable LPDDR design with the ability to support a wide range of high-bandwidth memory applications.
It includes sophisticated engines to rearrange transactions and maximize memory bus utilization. Programmable arbitration algorithms allow for multiple ports to share the memory bus efficiently. The Denali Controller IP for LPDDR4 is configurable to meet specific data profiles and enables performance optimization for an individual system and memory requirements.


Features : - Compliant to DDR 4/3/3L protocol memories
- Flexible paging policy including auto-precharge-per-command
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc
- Priority-per command on ARM AMBA3 AXI and low latency Denali interface
- QoS features allow command prioritization on ARM AMBA4 AXI interfaces
Categories :
Maturity : Silicon proven
Portability :
Type : Soft
Deliverables : - Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: integration and user guide, release notes
- Sample Verification testbench with integrated BFM and monitors
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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