CAST, Inc. 
Part Number : SPI-MS
Short Desc. : Master/Slave Serial Peripheral Interface Bus Controller Core
Overview :

Implements a synchronous serial data link controller that functions as either a master or a slave device over the standard Serial Peripheral Interface (SPI) Bus,

The SPI-MS bus controller can be configured under software control to be a master or slave device. Reading and writing the core is done via the AMBA® APB bus interface. The core operates in 8-bit, 16-bit, 24-bit, and 32-bit data modes. The data is then serialized and transmitted from master to slave device using the standard four-wire SPI bus interface.

The data is transmitted synchronously with the MOSI (Master Out, Slave In) relative to the SCLK generated by the master device. The master also receives data on the MISO (Master In, Slave Out) signal in a full duplex fashion.

The SPI-MS controller can be used with up to four slave devices. When the core is configured as a slave, the MISO signal is tristated to allow for multiple slaves to transmit data to the master when the slave is selected.

The SPI-MS core is proven and available in RTL source or as a targeted FPGA netlist.

Features : - Flexible SPI Master/Slave
- Software programmable Master or Slave mode
- Software programmable SCLK rate
- 8-bit, 16-bit, 24-bit, and 32-bit synchronous serial transmission
- Full duplex operation
- 16 word/byte Transmit FIFO (configuration option)
- 16 word/byte Receive FIFO (configuration option)
- AMBA APB interface
- Interrupt control
- LSB or MSB mode
- Up to four slaves under Master control
- Tristate Slave MISO signaling for multiple slaves
- Smooth Technology Mapping
- Fully synchronous, scan-ready, design architecture
Categories :
Portability :
Type : Soft
Deliverables : - Delivered with sample scripts, RTL test-bench and sample test-cases
S2C: FPGA Base prototyping- Download white paper

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