Cadence Design Systems, Inc. 
Part Number : IP1252
Short Desc. : DDR3/3L/DDR2/LPDDR2/3 LP Soft PHY up to 1333Mbps
Overview :
Our DDR DRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of your DDR application. The use of the Cadence synthesizable DDR PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
Features : - DDR PHY achieves up to 800 Mbps PHY including synthesis, layout, and timing closure in 4 hours using a standard EDA toolset
- Process node independent
- Configurable for data width, ECC, and DFI LPI options
Categories :
Maturity : Silicon proven
Portability :
Type : Soft
Deliverables : - Clear, readable, synthesizable RTL
- Verilog sample testbench with Cadence memory models, encrypted memory controller, and sample tests.
- Synthesis and STA Scripts
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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