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 Cadence Design Systems, Inc. 
Part Number : IP5034
Short Desc. : MIPI I3C Master Controller IP
Overview :

MIPI I3C Slave Controller IP – complete IP solution, fully verified on FPGA with a superior performance to simplify board design, and increase power efficiency.
Compliant with the latest MIPI I3C specification and backward compatible with I2C, the IP Controller for MIPI I3C is engineered to quickly and easily integrate into any mobile embedded system on chip (SoC) device and expand sensor communication capabilities with better power efficiency.
Rapidly increasing numbers of sensors creates new design challenges for mobile, automotive, and Internet of Things (IoT) devices. The Cadence Slave Controller IP for MIPI I3C delivers area-optimized interface IP with the low power and high performance required for leading-edge devices. It is suitable for design challenges that include significantly higher signal count and increased bandwidth requirements.
With MIPI I3C Slave Controller your customers can always be on the move, using applications with confidence and reliability.


Features : - Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR) Compliant with the latest I3C specification
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Optional support for user generic I/O signal registers
- Support for in-band interrupts, hot-join, peer-to-peer request, mastership request
- I2C legacy device support
- APB interface support for register access
- Command queue support
- Interconnect protocol
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - Documentation : Integration guide, user guide, and release notes
- Clean, readable, synthesize-able Verilog RTL
- Synthesis scripts
- Sample verification testbench with integrated BFM, monitors, and sanity tests
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