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 Cadence Design Systems, Inc. 
Part Number : IP5032
Short Desc. : MIPI I3C Master Controller IP
Overview :

The Master Controller for MIPI I3C IP - superior performance to power ratio compared to established sensor interfaces. Rapidly increasing number of sensors create new design challenges for mobile, automotive, and Internet of Things (IoT) devices. These challenges include significantly higher overall pin count and increased bandwidth requirements. To address these challenges MIPI Alliance has defined the I3C (SM) interface for connecting all sensors in the system with a single 2-wire high speed connection. Compliant with the MIPI I3C and legacy compatible with I2C specification, our Controller IP for MIPI I3C Master is engineered to quickly and easily integrate into any mobile embedded system on chip (SoC) device and expand sensor communication capabilities with better performance and power efficiency. With the Cadence Master Controller IP for MIPI I3C your customers can always be on the move, using applications with confidence and reliability.


Features : - Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR) Compliant with the latest I3C specification
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Optional support for user generic I/O signal registers
- Support for in-band interrupts, hot-join, peer-to-peer request, mastership request
- I2C legacy device support
- APB interface support for register access
- Command queue support
- Interconnect protocol
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - Clear, readable, synthesizable Verilog RTL
- Synthesis scripts
- Sample Verification testbench with integrated BFM and monitors
- Documentation - Design Specification, Verification Specification and Test Plan
TrueCircuits: UltraPLL



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