This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements a high-performance, ASIC or FPGA, hardware JPEG encoder that is very small in silicon area.
The JPEG-D-S Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.
The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 65,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.