CAST, Inc. 
Part Number : SHA-256
Short Desc. : 256-bit SHA Cryptoprocessor Core
Overview :

The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits.

Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option.

Features : - Designed according to the FIPS 180-2 Standard
- Maximum message length up to (264 – 1) bits
- Suitable for data authentication application
- Simple, fully synchronous, reusable design
- Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
- Complete deliverables include test benches, C model and test vector generator
Categories :
Tags : 256-bit SHA Cryptoprocessor Core
Portability :
Type : Soft
Deliverables : - HDLRTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench (self checking)
- C Model & test vector generator
- Simulation script, vectors & expected results
- Synthesis script
- User documentation
CST: Webinars Begin on February 9

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