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 CAST, Inc. 
Part Number : JPEG-DX-F
Short Desc. : Ultra-Fast Baseline and Extended JPEG Decoder Core
Overview :

This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.

The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.


Features : - 8/12-bit JPEG decoder for ASIC and FPGA with scalable, ultra-high performance
- Standards Support
- ISO/IEC 10918-1 Standard Baseline and Extended Decoder (Sequential DCT modes)
- Single-frame JPEG images and Motion JPEG payloads
- Up to four color components
- 8- and 12-bit color samples
- All widely used color-sub-sampling formats, and any image size up to 64k x 64k
- All scan configurations and all JPEG formats
- All marker segments expect DNL
- Up to four Huffman Tables
- Up to four b-nit or 18-bit Quantization tables
- Interfaces
- AXI Streaming I/O data interfaces
- APB Control/Status interface
- Optional AHB wrapper with DMA capabilities
- Performance
- Synthesis-time configurable scalable architecture
- Very high throughput: up to 32 samples per clock cycle
- Achieves maximum throughput when decoding streams produced by JPEG-EX-F
- Ease of Integration
- Requires no programming or control from host
- Reports image format
- Detects and reports marker syntax errors
- Delivered with bit-accurate software model
- Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer
Categories :
Tags : Ultra-Fast Baseline and Extended JPEG Decoder Core
Portability :
Type : Soft
Deliverables : - Verilog RTL source code
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
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S2C: FPGA Base prototyping- Download white paper



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