Part Number : dwc_ev64_processor
Short Desc. : EV64 processor for embedded vision applications with quad-core HS VDSP Vision CPU
Overview :

The DesignWare® EV61, EV62 and EV64 embedded vision processors are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware. The EV6x family features the most integrated vision processor solution available combining a high-performance 32-bit scalar core with a 512-bit vector DSP, an optimized CNN engine, and support for user-defined APEX hardware accelerators. The processors are highly scalable and configurable enabling users to tailor them to their specific application requirements to maximize performance while minimizing power and area. The optional CNN engine is a programmable object detection engine that implements a convolutional neural network (CNN) enabling fast and accurate detection of a wide range of objects such as faces, pedestrians and hand gestures. The EV61 features a single vision CPU (32-bit ARC® HS scalar CPU with a 512-bit wide SIMD vision digital signal processor), the EV62 features a dual-core vision CPU and the EV64 has a quad-core vision CPU. All three products can be configured with the optional CNN engine.

Features : - Optimized for high-performance embedded vision applications
- Based on advanced ARCv2 ISA
- Fast, accurate object detection with a programmable CNN object detection engine
- CNN engine delivers >1000 GOPS/W with 5X better power efficiency than competitive vision processors
- High-performance vision CPU with 512-bit wide SIMD vector DSP and 32-bit scalar CPU
- Single- dual- and quad-core vision CPU versions
- Supports data- and task-level parallelism
- Runs full range of vision algorithms
- Works with all host processors for vision offload
- High productivity MetaWare programming tools with OpenCV, OpenVX and OpenCL C Compiler
Categories :
Maturity : Available
Portability :
Type : Soft
Deliverables : - The DesignWare EV61, EV62 and EV64 Processors are delivered as Verilog HDL in the ARChitect IP Library
- The HDL is configured and output from the ARChitect IP Configurator tool
- To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included
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