OmniPHY Inc 
Part Number : OMNI_101001000_TSMC 90LP
Short Desc. : 10/100/1000 Gigabit Ethernet PHY IP, Industrial Extensions - 90LP
Overview :

OmniPHY’s Gigabit Copper Ethernet PHY is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer Transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair UTP Cable. 


• Laser/Network Printer 
• Network Attached Storage (NAS) 
• IPSet-topBox 
• GameConsole 
• Triple-play(data,voice,video)MediaCenter 
• MediaConverter 
• Network Server 
• Gigabit LAN on Motherboard (GLOM) 
• BroadbandGateway 
• Gigabit SOHO/SMB Router 


  • OmniPHY are the technical leaders in the "Ethernet PHY as IP" trend.
  • Our superior implementation skews the integrate vs discrete heavily in favor of low power integrated solutions.

Features : - Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications.
- Optimized per port area and power make the IP well suited to integration. The design includes the I/O pads necessary to implement the interface.
- DSP-based adaptive equalizer with baseline wander correction
- Auto-MDIX
- Low and deterministic latency
- A fully flexible interface – MII, GMII, RGMII
- WOL, Energy detect mode, Sleep mode, Power back-off modes
- Available in Single-Port and Dual-Port configurations
- Multiple temperature ranges (option)
- EMC/EMI optimized
- Leading-edge jitter tolerance
- Built-in-self-test including pattern generator/checkers and built in error counters
- Forced link-up and fast link-down modes
- Polarity correction (10Base-T mode)
- SMI pre-amble suppression and next page support
- Pin-strapping options for fast configurations
- Options for industrial:

- Extended cable reach (as an option, up to 130m)
- Patent-pending self-monitoring techniques, including signal quality monitoring
- Extended temperature ranges
- IEEE 1588 hardware support
- Hardware-based cable diagnostics
Categories :
Maturity : Silicon Proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :

Deliverables : - GDSII - compliant with DFM
- .LEF
- LIBERTY files for timing closure
- verilog
- netlist
- extensive documentation
S2C: FPGA Base prototyping- Download white paper

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