Implements an Inter-Integrated Circuit (I2C) Bus slave controller that meets the Phillips I2C version 1.4 specification.
Under its default configuration, the I2C-S provides access to its 8-bit-wide status and control registers via an APB-slave port. Alternatively, the core can be equipped with an AHB-slave, Wishbone-slave or generic microcontroller interface.
The I2C-S allows dynamic control of the serial clock frequency, and the I2C bus speed is only limited by the external bus driver capabilities. The I2C slave 7-bit address is programmable, and the core uses FIFOs for transmit and receive data to reduce the host overhead. Being accompanied by a low-level C-driver, the I2C-S core enables easy and rapid development of over-I2C, or I2C-like protocols in user applications.
The I2C-S is production proven in ASIC and FPGA technologies.